1. Field of the Invention
The invention relates generally to sputtering of materials in the fabrication of semiconductor integrated circuits. In particular, the invention relates to copper sputtering.
2. Background Art
Copper is rapidly replacing aluminum as the preferred metallization in advanced semiconductor integrated circuits. Metallization is used to form electrical interconnects extending horizontally in usually multiple wiring levels and extending vertically between wiring levels. Such vertical interconnects are usually called vias. Similar vertical connections to an underlying silicon layer are usually called contacts and require additional barriers and contact layers, but for many purposes of this invention, they may be considered as vias. Copper is advantageous for metallization because, among other reasons, it has a lower electrical resistivity and is less subject to electromigration than aluminum. It is understood that the copper used for metallization need not be pure but may be doped with alloying elements such as magnesium and aluminum or other intentional or unintentional dopants to less than 10 wt %. Copper presents challenges as well as the stated advantages over aluminum.
Aluminum etching techniques are well developed to define the horizontal wiring and to restrict the aluminum to the via area, but copper has proven to be difficult if not impossible to etch in a commercial environment. Instead, damascene processes have been developed to define the interconnects. As illustrated in the cross-sectional view of FIG. 1, a lower-level dielectric layer 10 is typically formed of a material based on an oxide of silicon, hence its common name of oxide layer. Conductive features 12, 13, such as copper features, are formed in a surface of the lower-level dielectric layer 10. An inter-level dielectric layer 14 is deposited as a planar layer over the lower-level dielectric layer 10 and its conductive features 12, 13. In the case of single damascene, a through via hole 16 is etched through the inter-level dielectric layer 14 over the conductive feature 12 to be electrically contacted. In the case of dual damascene, a more complex hole is etched including a bottom via hole 18 in the lower portion of inter-level dielectric layer 14 over the conductive feature 13 and a wider trench 20 in its upper part connected to the via hole 18.
The via holes 16, 18 typically have a circular shape of minimum width, approximately 0.13 μm in current advanced technology, and provide the vertical interconnects. On the other hand, the trench 20 has a larger rectangular shape that may extend a significant distance, perhaps millimeters, perpendicularly to the plane of illustration to provide a horizontal interconnect perhaps contacting multiple conductive features in the lower-level dielectric layer 14 through respective vias 16. The copper-filled through via 16 and trenches 20 also provide conductive features or pads to a yet higher level of wiring. An isolated pad of circular shape may be formed instead of the trench for a connection straight through the dielectric. In any case, the minimum width of the pad or via is greater than the minimum width of the underlying via in a ratio of at least 1.5 and usually at least 2.0. The etching of the complex dual-damascene structure of the trench 20 and connected via 18 may be done in a number of well known ways, typically involving an unillustrated etch stop layer, for example, of silicon nitride formed midway in the inter-level dielectric layer 14. Another unillustrated etch stop layer may underlie the lower portion of the inter-level dielectric layer 14 to define the lower limit of via etching. The same wiring level may include both through vias 16 for single damascene and bottom vias 18 and trenches 20 for dual damascene, which are simultaneously etched and filled.
Direct contact of the copper metallization to the oxide dielectric should be avoided because copper can diffuse into the oxide, potentially causing electrical shorts through the dielectric material, and oxygen can diffuse into the copper, reducing its electrical conductivity. Hence, a thin, typically conformal barrier layer 22 is coated onto the sides of the via holes 16, 18 and trench 20 though it is preferably removed from the bottom of the via holes 16, 18 to reduce contact resistance to the conductive features 12, 14. For copper metallization, tantalum nitride (TaN) is the preferred barrier material that blocks the diffusion of either copper or oxygen through it. A metallic tantalum layer is sometimes included for adhesion, often on the copper side. Other barrier materials, typically involving a refractory nitride such as TiN or WN, have been suggested, and more complex barrier structures than a Ta/TaN bilayer have also been suggested.
The fundamental concept in a damascene process is that the metallization, here copper, is deposited to not only fill the via holes 16, 18 and the trench 20 but also to cover the top surface 24 of the inter-level dielectric layer 14. Chemical mechanical polishing (CMP) is then used to remove the copper extending above the level of the single-damascene through via 16 and the dual-damascene trench 20. Because oxide is much harder than copper and has a different type of chemical bonding, the CMP process can be tuned to stop on the top oxide surface 24 after the overlying copper and usually the barrier material have been removed. As a result, the copper is confined to the vias 16, 18 and the trench 20 to form both the vertical interconnects through the vias 16, 18 and the horizontal interconnects and pads in the trenches 20.
The process for depositing copper or tantalum faces the difficulty of coating and eventually filling via holes having high aspect ratios, that is, the ratio of depth to minimum width. As mentioned before, via widths of 0.13 μm represent current advanced technology, and further and significant decreases in the critical dimension are being planned. On the other hand, the thickness of the inter-level dielectric is constrained to be no less than about of 0.7 μm or even greater for more complex structures in order to avoid or minimize cross-talk and dielectric breakdown. Therefore, the aspect ratio of holes to be filled is 5 or greater, and this value will only increase in the future.
Sputtering a metal in a physical vapor deposition (PVD) process to fill such high aspect-ratio holes presents inherent difficulties since sputtering is fundamentally a ballistic process ill suited for reaching the bottom of such deep and narrow holes. As illustrated in the cross-sectional view of FIG. 2, if conventional techniques without further embellishments are used to sputter a metal layer 30 into a high aspect-ratio hole 32 formed in a substrate 34, the metal, whether copper or tantalum, preferentially deposits on the upper corners of the hole 32 to form overhangs 36, which in turn are at least partially responsible for localized thin areas 38 on the via sidewalls. The overhangs 36 cause several difficulties. If only a relatively thin metal layer 30 is being deposited, the thin areas 38 must be thick enough to act as a barrier or seed layer and not to agglomerate, leaving portions of the underlying layer exposed. To assure a minimum thickness of a few nanometers requires depositing a significantly thicker layer in other portions of the sidewall. However, the additional sidewall thickness further increases the effective aspect ratio of the via hole, and the overhangs 36 further and significantly increases the effective aspect ratio. If sputtering is used to fill the via hole, the overhangs 36 may grow to the point that they bridge over before the bottom of the hole 32 is filled. As a result, deleterious voids will form.
Ionized sputtering, whether ionized metal plating (IMP) or self-ionized plasma (SIP) sputtering, produces a significant fraction of the sputtered copper atoms that are ionized. Both processes rely on high-density plasmas. Ionized metal plating typically inductively couples additional RF energy into the chamber and operates at higher pressures. SIP sputtering uses other techniques to achieve a higher-density plasma at significantly lower pressures. If the wafer being coated is negatively biased, the positive copper ions can be drawn deeply into narrow holes. However, it has been conventionally felt that ionized sputtering into very narrow holes will still produce excessive overhangs while reducing sputter deposition into the bottom of the high aspect-ratio holes with the resultant formation of voids.
Nonetheless, metal ions of higher energy tend to not stick to the surface being struck but instead bounce from it. Further, above a metal ion energy of about 100 eV, the metal ion does not deposit but begins to sputter etch the feature it is striking. The exposed geometry of the overhangs 36 makes them particularly prone to being sputter etched. Thus, if the wafer biasing is further increased, the overhangs 36 are deposited less and may even be preferentially etched while less exposed locations are being deposited with sputtered material. However, the sputter etching of the corners needs to be carefully controlled since excessive ion energy goes beyond zero deposition and instead begins to etch the underlying layer at the geometrically exposed corner of the hole. For barrier metal sputtering, zero deposition means no barrier at the corner. For copper sputtering, net removal may remove the corner barrier and expose the underlying oxide to the copper or in a less extreme case produce a discontinuous copper seed layer.
In the dual-damascene structure of FIG. 1, lower corners 40 between the via 18 and the trench 20 are more prone to serious problems than upper corners 42 at the top of the trench 20. The upper corners 42 are exposed to a more isotropic and neutral and hence lower-energy flux of sputtered atoms. Hence, they tend to develop greater overhangs but even with high biasing are not so subject to beveling. Further, the upper corners 42 are subsequently processed by CMP and often covered thereafter with another barrier layer, thus being to some degree repaired. On the other hand, the lower corners 40 are at least partially shielded from the isotropic neutral flux and are more exposed to beveling by high-energy ions. Further, the lower corners 42 are covered by the copper fill during the subsequent processing so that any beveling is preserved. The open geometry of dual damascene reduces the overhang problem, but the lower corners 42 are more subject to beveling because of the reduced low-energy neutral flux. However, overhang continues to be a problem when through vias are simultaneously processed.
Chemical vapor deposition (CVD) may be used to coat nearly conformal layers in high aspect-ratio holes, particularly of the barrier metal and its nitride. However, PVD is preferred despite its tendency for non-conformality because of its lower cost and higher quality of the deposited films.
Electro-chemical plating (ECP) has recently been significantly developed to complete the copper fill. ECP is a wet electrolytic process in which a liquid electrolyte containing copper ions flows into the narrow holes and deposits copper nearly conformally on the sides and bottoms of high aspect-ratio holes. ECP has several advantages beyond its conformality. It deposits relatively quickly and uses a primarily inexpensive source of copper. Despite its popularity, however, ECP has several disadvantages. It is a wet process which is difficult to integrate with the dry plasma processing in a clean room associated with most of the rest of semiconductor fabrication. Its incompatibility with clean room operation complicates the production queue. Further, since ECP is an electrolytic process depositing onto a dielectric under layer, it is necessary to provide an electrode layer over the dielectric. Nitrides in the barrier layer are insufficiently conducting for this purpose, and even the refractory metals exhibit poor conductivity. As a result, a thin conformal copper seed layer is conventionally deposited on top of the barrier layer to not only act as a plating electrode but also to nucleate the ECP copper while adhering to the nitride barrier. Ionized sputtering of copper performed on wafers held at less than 50° C. has proven effective at forming the copper seed layer. At a minimum, ionized sputtering, when used to form thin copper seed layers, is not so subject to overhangs because only such a small amount of copper needs to be deposited that is insufficient to produce bridging. However, its thickness must be great enough to uniformly cover the dielectric over the vertical extent of the hole. At via diameters of 0.13 μm and below, the combined thickness of the barrier layer and the copper seed layer further narrows the hole, increasing its effective aspect ratio. Any overhangs, particularly of the seed layer, further increases the effective aspect ratio of the remaining portion of the hole to be coated or filled. The copper seed deposition also introduces an additional process step.
Finally, ECP may not be sufficient for filling the very high aspect-ratio holes anticipated for processing at 90 nm and below. If any overhangs exist from the barrier or seed layer deposition, the generally conformal ECP deposition may cause the top of the hole to bridge over before the bottom of the hole is filled, thereby creating voids in the via metallization. Further, ECP relies upon the flow of fresh electrolyte into the hole and the removal of depleted electrolyte from it. Since electrolyte replenishment is more effective at the top of the hole, ECP is likely to form its own overhangs which may close the hole before the hole is filled. That is, voids in the copper may still develop with ECP. To avoid these problems, both the ECP equipment and the electrolyte used for copper electro-plating have become increasingly more complex, expensive, and difficult to use. It is felt that copper fill utilizing ECP as presently practiced does not solve the problems of future generations of integrated circuits.
Ding et al. in U.S. Pat. No. 6,184,137 describe a copper fill procedure utilizing primarily copper sputtering in which the fill is only incompletely performed such that a thin capillary is formed to extend vertically down the center of the via hole. The copper is then reflowed at above 450° C. to fill the capillary. Ding et al. in published European Patent Application EP 0 878 843 A2 describe a multi-step copper sputtering process involving different temperatures. Chiang et al. in U.S. Pat. No. 6,398,929 disclose a copper seed layer deposited by SIP followed by a higher-temperature sputter deposition of copper.
There is much prior art for cold/hot aluminum sputtering processes, but this work is not obviously transferrable to copper sputtering because copper's melting point of 1093° C. is much higher than the 660° C. of aluminum, the higher temperature being totally incompatible with previously formed structure such as shallow dopant implant profiles, thin gate oxides, and organic low-k dielectrics while the lower temperature is much closer to temperatures tolerable by these features.